Research : Papers

Refereed Publications

Terauchi, Tachio and Megacz, Adam  Inferring Channel Buffer Bounds via Linear Programming, proceedings of the 17th European Symposium on Programming (ESOP'08). [doi] [bib] [software]

Megacz, Adam,  A Coinductive Monad for Prop-Bounded Recursion [ slides] (2007) in Proceedings of ACM Programming Languages meets Program Verification 2007 (PLPV'07). [doi] [bib] [software]

Megacz, Adam,  A Library and Platform for FPGA Bitstream Manipulation (2007) in Proceedings of IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'07).  (slides) [doi] [bib] [software]

Megacz, Adam,  Scannerless Boolean Parsing, Electronic Notes in Theoretical Computer Science 1368, (Volume 164, Issue 2): Proceedings of the Sixth Workshop on Language Descriptions, Tools, and Applications (LDTA 2006). [doi] [bib] [software]

Alliet, Brian and Megacz, Adam,  Complete translation of unsafe native code to safe bytecode., In Proceedings of the 2004 Workshop on Interpreters, Virtual Machines and Emulators (IVME'2004, now known as VEE), Washington, D.C. ACM Press, New York, NY, 32-41. [doi] [bib] [software]

Research Statement

A programming language is a compromise between what a machine can execute efficiently and the terms in which a human is able to express algorithms easily. Assembly language lies at one end of this spectrum, and scripting languages at the other. My long-term research interest is exploring the contour of this compromise and finding ways to improve it.

Current Focus

My current research topic is figuring out how to program Fleet, a highly concurrent, communication-oriented, clockless zero-core processor.

A Fleet processor consists of an extremely fine-grained on-chip network which connects simple functional units such as adders and storage fifos. The granularity of the network is such that the functional units themselves are generally not programmable; the operation of the machine is coordinated by programming the network itself. This is in contrast to other on-chip networks, which typically connect individually-programmable units or “cores” at a much coarser granularity.

The main challenge in programming Fleet arises from the fact that a word in on-chip storage is identified not by an address — as in caches and register files — but by its position in a sequence or, more generally, in a causal partial ordering. This perspective shift has enabled architectural choices that give Fleet tremendous throughput, but has also disqualified programming models which assume the ubiquity of pointers or references.

My present focus is on functional programming over bulk pointerless data as a tractable framework for programming Fleet. I am currently experimenting with extensions to Java which offer these capabilities; the extensions are patterned after Haskell and ML. My work draws from the rich literature on nested data parallelism and the vector RAM model, but de-emphasizes the permute operator and includes concurrency (control parallelism) and pipeline parallelism.

Other Interests

• Parsing technologies, including scannerless parsers, boolean grammars, and generalized LR parsing.

• Interactive theorem proving, formal methods, type theory.

• Non-von Neumann machines.

• I try to keep up to date with the literature on the following topics, although I do not actively do research on them: uniqueness types, “the awkward squad”, garbage collectors, distributed filesystems.

Obsolete

Here are some things that I never quite finished, but people have asked about. Please consider everything below to be incomplete/unpublished work.

Meta-HDL was an effort to generate circuits using MetaOCaml. Here are some links to the  unpublished paper and unfinished source code.

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